PIN DIAGRAM OF 8085

Microprocessor 8085 is a 40-pin IC which operates on +5 V power supply and 3 MHz frequency. 

These 40 pins are divided into six groups according to their functions. These groups are: 

1. Frequency and power supply signals 

2. Higher order address bus 

3. Multiplexed address/data bus 

4. Control and status signals 

5. Serial IO signals

6. Externally or peripheral initiated signals. 

PIN DIAGRAM OF 8085

We will discuss each group one by one.

GROUP 1 : FREQUENCY AND POWER SUPPLY

X1, X2 (Input) 

These are the two input lines across which a Crystal or R/C oscillator circuit is connected to provide the required clock frequency to the microprocessor. The frequency generated by the oscillator is divided by 2 to give the internal operating frequency of the microprocessor. The input frequency is divided by 2 because the frequency is applied to the system through a flip-flop which divides the incoming frequency by 2. 

V_cc

+5 Volt Supply

V_ss

Ground Reference

Group 2: A8-A15, Higher Order Address Bus (Output) 

Instead of having 24 pins for address and data lines, 8085 has only 16 pins. Out of the 16 pins, 8 pins are used to carry the higher order address and the other 8 pins are multiplexed to carry the address as well as the data. This multiplexing is done to keep the number of pin as minimum as possible. 

A8 - A15 carries the most significant 8 bits of the address.

Group 3: AD0—AD7, Multiplexed Address/Data Bus

These lines are time multiplexed with the lower 8-lines of the address bus. Lower 8-bits of the memory address or IO address appear on the bus during the T, state of a machine cycle. It then becomes the data bus during the second and the third clock cycles. 

Group 4: Control and Status Signal

ALE (Address latch enable) (output)

ALE as its name suggest, enables the address latch to store the address during the demultiplexing operation. It occurs during the first T state of every machine cycle. 

Whenever microprocessor sends a valid address on the multiplexed lines, it also make the ALE signal high.

RD (read) (output)

Read is an active low output control signal. When this signal is low, it indicates that the microprocessor wants to read a data either from memory or IO device. Generally Microprocessor activates this signal during the T2 state of the machine cycle. This shows that in this state, the data bus is ready to carry the data.

WR (write) (output)

Write is an active low output control signal. When this signal is low, it indicates that the microprocessor wants to write a data either into memory or IO device. 

IO/M (output) 

The Read and Write signals indicates that the microprocessor wants to read or write a data but do not specify from where this read or write operation will take place. This is indicated by the IO/M signal. When this signal is low, it means a read or write operation will take place from/to memory. When this signal is high, it means the operation is with reference to IO. 

So, S1, (status signal) (output) 

These are the two data bus status signals. The four combinations of these signals give the information of what the microprocessor is doing or the encoded status of the bus cycle. The four status information represented by these status signals are tabulated in Table below.

S1	S0	Opearion
0	0	HALT
0	1	WRITE
1	0	READ
1	1	FETCH

GROUP 5 : SERIAL IO SIGNAL

SID (input) 

Stands for Serial input data. This line is used in serial data communication. Through this pin,  serial data is received by the processor. The data on this line is loaded into accumulator bit whenever a RIM instruction is executed.

SOD(output)

Stands for Serial Output Data. This line is used in serial data communication Through this pin the serial data is transmitted by the processor The output SOD is set or reset as specified by the SIM instruction.

Group 6: Externally or Peripheral Initiated Signals

TRAP (Input) 

Trap is a non-maskahle interrupt which have the highest priority. This interrupt cannot be masked or disabled. This is a vectored interrupt. It is edge as well as level triggered.

RST 5.5, RST 6.5, RST 7.5 (inputs) 

RST7.5 has the highest priority and it is edge triggered.

RST6.5 is level triggered.

RST5.5 has the lowest priority and it is level triggered.

The priority of these interrupts is ordered as shown. All these have higher priority than INTR

INTR (Interrupt request) (input) 

INTR is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of an instruction cycle. When it is active, the Program Counter (PC) will stop incremented and an interrupt acknowledge signal is issued by the processor. 

INTA (interrupt acknowledge) (output)

This signal is generated by microprocessor in response to the INTR. When microprocessor accepts the INTR, it executes an INTA machine cycle.

READY (input) 

This signal is used to synchronize the slower peripherals with microprocessor. If 'Ready' is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If 'Ready' is low, the CPU will wait for 'Ready' to go high before completing the read or write cycle.

HOLD (hold request) (input) 

HOLD is bus request from a competent bus master. Whenever a competent bus master like DMAC (Direct memory access controller) wants to transfer data between memory and IO, it sends a request on the HOLD pin of the microprocessor. On receiving the Hold request signal, the microprocessor suspends its current operation and relinquishes the buses as soon as the completion of the current machine cycle. 

HLDA: HOLD acknowledge (output) 

On receiving the HOLD request, the microprocessor completes the current machine cycle and then suspends its operation, release the buses and sends a HOLD acknowledge signal to the DMAC. 

HLDA goes low after the Hold request is dropped.

RESET- IN (input)

This signal is used to reset the processor. When microprocessor receives a signal on this pin it clears the Program Counter and resets the Interrupt Enable and HLDA Flip-flop. Except the Instruction register, all the general purpose data registers and the flag register remain unaffected by the Reset signal. 

RESET OUT (output) 

This signal is used by the microprocessor to reset its peripheral devices. It can be used as a system RESET. The signal is synchronized to the processor clock. 

CLK (output)

Clock output is used as a system clock when a crystal or R/C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. 

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